As data is transmitted over a channel from a serializer device to a deserializer device, loss in the channel results in the amplitude being attenuated and inter-symbol interference (ISI). These issues are exacerbated as data transmission speeds increase.
An important element of the deserializer device is a decision feedback equalizer (DFE). A DFE processes an input stream DIN of data to yield an output stream DOUT of data. The input stream DIN represents input bits {b1, b2, b3, . . . }, and the output stream DOUT represents output bits {B1, B2, B3, . . . }. To compensate for the ISI, the DFE adjusts each input bit using N previous output bits to yield the corresponding output bit, where N is a positive integer. Mathematically, this is expressed as
      B          N      +      1        =            b              N        +        1              +                  ∑                  k          =          1                N            ⁢                        α          k                ⁢                  B          k                    where the coefficients αk express the strength of the contribution of the kth previous output bit Bk to the adjustment.
More specifically, the DFE adjusts the voltages representing each input bit by the voltages representing N previous output bits to yield voltages representing the corresponding output bit.
N latches of the DFE store the N previous output bits. Each one of N taps determines the coefficient α that expresses the strength of the adjustment contributed by a corresponding one of the previous output bits. A summing node of the DFE samples the input bit and adds the adjustments to the sampled input bit.
It is common to implement the latches of a DFE using current mode logic (CML). K-L J. Wong, A. Rylyakov, and C-K K. Yang, “A 5-mW 6-Gb Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions”, IEEE Journal of Solid-State Circuits, vol. 42, no. 4, April 2007 describes using a quarter-rate CML-based DFE to make clock generation and distribution simpler.
B. Ravazi has shown in “Charge Steering: A Low-Power Design Paradigm”, Custom Integrated Circuits Conference, pp. 1-8, September 2013 that latches based on charge-steering (CS) techniques demonstrate power savings of approximately 4.4 times the CML latches.
The CS equalizers described in A. Manian and B. Razavi, “A 40-Gb/s 14-mW CMOS Wireline Receiver”, IEEE Journal of Solid-State Circuits, vol. 52, no. 9, September 2017, require extensive distribution of half-rate clocks, which make their design inappropriate for pushing data transmission speeds.